In conventional A/V information household electronic appliances, a bus system transfers two different kinds of data, i.e., a first kind of data to be transferred isochronously or in real time, such as an A/V stream of data, and a second kind of non-isochronous or regular data. The control for maintaining the isochronism of the isochronous transfer is performed by software of the bus system. Hardware of the bus system only manages a grant of the bus to each node at each transfer cycle. Thus, the software manages how a plurality of isochronous transfers of data should be performed and what amounts of regular transfers of data are generated, and then controls the sequence of the plurality of data transfers and controls each isochronous transfer in a sufficiently small unit of data so as to prevent a failure in the isochronous transfers. In a bus system in compliance with the isochronous data transfer of IEEE 1394, periods of time for isochronous data transfer are reserved periodically. In any types of the bus systems, in order to prevent buffer overflow and underflow in the isochronous transfer, the bus is typically operated at the maximum operating rate of the bus or at the operating rate specific to each node. In a bus system without requirements for provisions of such isochronous transfer, in order to reduce the power consumption of the bus system, the operating rates and the operating voltages of the entire bus system may be changed in accordance with the statistics or the like of accesses to the bus, or alternatively the power supply itself may be frequently turned on and off.
Japanese Patent Application Publication JP 2000-20458-A describes a bus control circuit. In this bus control circuit, an arbiter has the functions of: monitoring a control signal and a data line in accordance with a signal from a bus monitoring circuit of a bridge that indicates the operating state of the bus; monitoring another control line and another data line in accordance with another signal from the bus monitoring circuit; and thereby issuing a grant to each channel device for a transaction start request. The arbiter controls the two data lines to operate as 32-bit PCI buses or as a 64-bit PCI buses. When the data lines are operated as the 32-bit PCI buses, the arbiter controls two 32-bit channel devices to use the respective different 32-bit PCI buses.
Japanese Patent Application Publication JP 2003-30133-A describes a bus type arbitration system. In this system, a bus arbiter determines the bus efficiency of functional blocks and control blocks connected to the bus, then assigns data transfer band width of the bus to the functional blocks and a CPU so that an expected value of the data transfer rate should be satisfied, and thereby satisfies the data transfer rate of the bus required in the system in real time. Further, in accordance with the requirements of the system, the CPU determines the expected values of data transfer rates of the bus for the functional blocks and the CPU, and then registers the values with the bus arbiter.